International Journal of Advanced Research and Development

ISSN: 2455-4030

Vol. 1, Issue 11 (2016)

Performance analysis of an efficient reversible design of BCD adder

Author(s): M Anusha, TL Spandana
Abstract: At Present the vlsi plays a major role for low power constraints devices like processors in the processing unit multipliers and adders makes a crucial role not only for low power but also low area and low delay in the present paper reversible logic gates are used for reversible operation The important reversible gates like Faynman Gate, Fredkin gate, toffoli gate, MTSG gate, CNOT gate and peres gate etc with the help of normal logic gates the complexity of the gate delay can be increased and power will be more so to over come these parameters in this paper the 4bit BCD can be designed the reversible operation can be applied so the low power can be obtained as well as delay the comparison shows the how much power is consumed by using reversible logic design the simulation and synthesis can be obtained using Xilinx tool.
Pages: 39-44  |  966 Views  267 Downloads
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