Vol. 2, Issue 2 (2017)
Design and simulation of low area and low delay modified 32-BIT SQRT carry select adder
Author(s): CH. Sandeep, Dr. GV Sridhar
Abstract: In present scenario vlsi plays a major role in many analog and digital circuits the performance of the processor has became high power, low speed and high area so overcome these parameters the multipliers and adders plays a crucial role in many digital signal processors In the present approach carry select adder (CSLA) is one of the fast adder used in many digital signal processing applications as well as ALU when compare to carry look ahead adder the CSLA occupies low area and high speed. From the structure of the CSLA, there is scope for reducing the area and delay in the CSLA. The thesis uses a simple and efficient gate-level modification to significantly reduce the area. In the present paper modified 32 bit SQRT CSLA is compared with the 32-bit conventional SQRT CSLA architecture. In the present paper the modification is done using binary to excess code converter technique (BEC-1) by replacing with the RCA stage of conventional method of 32 bit CSLA. The design is checked synthesized and simulated on Xilinx ISE design suite 14.1. The area comparison is done in respect of LUTs. Proposed design has reduced area and delay as compared with the conventional SQRT CSLA with only a slight increase in the delay. The thesis evaluates the performance of the design in terms of area and delay. The result shows that the modified SQRT CSLA structure as performed low area and low delay when compared to conventional SQRT CSLA.