Design of low area static CMOS parallel self-timed adder with low power consumption using conditional approach
G Siva Sai Narayana, KV Ganesh
Adder is an important circuit used in arithmetic and logic unit and many other applications. There are different types of algorithms used in adders to achieve better performance, low Area and low Power. The main objective of this paper is to provide new low power, area efficient solution for very large scale integration (VLSI) Circuit designers. We have many logic styles such as Swing Restored complementary Pass-transistor Logic (SR-CPL) and Dual Pass-Transistor (DPL), dynamic logic and static logic. Adder has been designed by using Static CMOS logic and it has the disadvantage of more Transistor count. We will also ensure that speed will not be worse by making sure that not more than four number of transistors are in series either in pull-up or pull-down network of CMOS. Cells which were being used has limited fan-in as well as fan-out, though asynchronous logic is employed. The proposed Adder has been designed and simulated by using TANNER EDA Tool.